Mina M.

Experienced Digital IC Design Engineer and RTL Coding Expert, SoC specialist offering FPGA/ASIC RTL Coding in Verilog, SystemVerilog, and VHDL, with Multilingual Tutoring. Available Round-the-Clock | Flexible Pricing | Prioritizing Service Excellence My Experience: I've worked extensively with CPUs, Computer Archecture, Digital Electronics, Assembly Languages and HDL coding. For ASIC design, I've harnessed the power of Synopsys tools, employing both TCL scripts and GUI. I am also proficient in documenting designs using three methods: LaTeX, and Microsoft Word. My portfolio showcases a diverse array of complex designs across fields like image processing, cryptography, communication protocols, and processors, all implemented using HDLs. Reach out to discuss the details, and I'll be here to assist you at any time. Your success is my priority. Key Skills: - Digital IC design - RTL Coding using Verilog/SystemVerilog and VHDL - Simulation and debugging using QuestaSim/ModelSim - Computer Archecture design (ARM, RISC-V, X86) and Assembly Language coding. - FPGA/ASIC flow - Communication protocols such as: UART - SPI - I2C - AXI - Programming languages such as: Python • C/C++. - Knowledge in scripting Language : TCL. Through these skills and various projects I have improved my technical skills, applied my knowledge and grown my network with people around the globe. Tools: Vivado IDE • Quartus prime • VS Code • Xilinx ISE • ModelSim/QuestaSim • Synopsys Deesign Compiler •MATLAB • Git/GitHub • Notepad++.