Vu L.

Senior FPGA engineer with 10+ years of hands-on design and verification experience, specializing in high-speed networking, SoC development, and open-source FPGA frameworks. Recent work includes: - 5G O-RAN Fronthaul on Xilinx UltraScale+ (eCPRI, 25G Ethernet, JESD204B) - RISC-V SoC debug transport over PCIe on AMD Alveo (LitePCIe, LiteX/Migen) - Ethernet packet scheduler and rate limiter using LiteX/LiteEth (10G, AXI4-Stream) Core strengths: - FPGA platforms: Xilinx/AMD UltraScale+, Alveo, Kintex, Artix · Zynq-7000 · Intel/Altera Cyclone - High-speed interfaces: 10G/25G Ethernet, PCIe (XDMA, LitePCIe), JESD204B, GTH/GTY - Frameworks: LiteX/Migen, Cocotb, Vivado, Quartus - Protocols: AXI4/AXI4-Stream, Wishbone, O-RAN 7.2x, IEEE 802.3, PTPv2 - Verification: UVM, Cocotb, formal verification (VC-Formal, JasperGold), VCS, Xcelium - Languages: SystemVerilog, Verilog, Python, C Available for remote engagements. Comfortable working async across time zones.