Muhammad B.

I'm an FPGA and embedded engineer who takes digital hardware from spec to working bring-up on real boards, architecture, RTL, verification, synthesis, timing closure, and on-board validation. On the FPGA side I write production-grade Verilog/SystemVerilog, build and debug designs in Vivado and Vitis (also ISE and Quartus when a project needs them), and target Xilinx Zynq-7000, Zynq UltraScale+, Artix/Kintex-7, and Lattice parts. Day-to-day work: clean RTL (FSMs, pipelining, CDC), AXI4/AXI-Lite/AXI-Stream SoC integration, custom IP, and constraint/timing closure on designs that have to actually meet Fmax, not just simulate. Verification is part of the job, not an afterthought, SystemVerilog testbenches, functional and code coverage, and assertions. I simulate in ModelSim/QuestaSim, Verilator, and Icarus, and debug on hardware with ILA, logic analyzer, scope, and JTAG. I go deep on RISC-V: custom RV cores, ISA extensions, and emulators, including instruction-set modification and syscall/binary remapping at the userspace level. On the embedded side I write C/C++ for microcontrollers and Linux, work with the GCC/LLVM toolchain, and handle interfaces like UART, SPI, I2C, DMA, PCIe, and Ethernet. If you have hardware or low-level software problems or need a new solution, send the spec and I'll reply with a clear scope and timeline.