Karthik M.

I design and verify digital hardware in SystemVerilog, from spec to RTL to a passing testbench, and I've taken a design through to tapeout. What I can do for you: • RTL design: pipelines, FSMs, caches, datapaths, and custom accelerators in Verilog/SystemVerilog, written to synthesize cleanly. • Verification: cocotb and UVM-style testbenches with Python reference models, scoreboards, constrained-random stimulus and coverage. • Sign-off checks: lint, CDC/RDC and formal runs (Synopsys SpyGlass), plus scripts that turn them into repeatable regressions. • Open-source ASIC flow: Yosys, OpenLane and SKY130, from RTL to GDSII with STA and DRC. • FPGA: Intel Quartus and Terasic DE10-Lite bring-up. Recent work: • RISC-V CPU IP: RV32IM 5-stage pipeline with forwarding and hazard logic, a 2 KiB 4-way write-back L2 cache, and a 256-MAC INT8/INT16 NPU unit. Verified in cocotb against a Python model. • MOESI cache controller: heterogeneous L1 controller serving CPU, GPU and NPU agents. Fixed 13 RTL bugs to get every test passing, and added cycle-accurate performance counters. • FFT accelerator: runtime-configurable 128/256-point streaming FFT with ping-pong memory, in SystemVerilog. • I2C controller tapeout: Verilog to GDSII with OpenLane on SKY130, accepted for the Google-SkyWater-Efabless MPW shuttle. • Industry, PCIe subsystem sign-off (2 yrs): lint, CDC/RDC and formal on high-throughput PCIe IPs. Fixed multi-bit CDC violations and automated the runs with Bash. • Past Upwork client: cocotb verification for a RISC-V server CPU startup (2022-23). Tools: SystemVerilog, Verilog, Python, cocotb, UVM, VCS, QuestaSim/ModelSim, Icarus Verilog, GTKWave, SpyGlass, Design Compiler, Yosys, OpenLane, Quartus, Git, Docker, Bash, TCL. Background: MS in Electrical & Computer Engineering, Purdue. Former graduate TA, and I write clear documentation and design reviews. Send me your spec or failing test. I'll reply with how I'd approach it.