Abdur Rehman K.

I’m an FPGA design engineer with 5 years of experience building RTL and complete SoC systems on Xilinx Zynq-7000, Zynq UltraScale+, Kintex UltraScale+ and Kria. I’ve delivered projects for clients in the USA, UK, Croatia and Italy, taking designs from architecture through to hardware debug. WHAT I DO 1- High-speed interfaces: custom PHY/MAC links, source-synchronous LVDS/DDR I/O, PCIe, clock domain crossing and lane deskew 2- Timing and debug: timing analysis, constraint work and in-system debug with ILA 3- Camera and video pipelines: MIPI CSI-2 capture and analysis, multi-camera systems, AXI Stream/AXI-DMA streaming, H.264 encoder integration 4- Algorithm-to-RTL: turning Python or MATLAB models into verified Verilog/VHDL, including image processing blocks 5- SoC design and bring-up: PS-PL integration, MicroBlaze, AXI4 interconnect and custom board bring up RECENT WORK 1- Designed a custom 32 Gbps PHY/MAC data link between two Zynq UltraScale+ boards (32 LVDS lanes at 500 MHz DDR, manual lane deskew with IDELAY/ODELAY and MMCM) 2- Built a passive MIPI CSI-2 analyzer on Kria K26 that rebuilds frames, metadata and timing from raw sensor lanes 3- Developed a real-time IR centroid detection video pipeline on Kria KV260, verified against a Python model 4- Delivered a dual-camera MIPI CSI-2 acquisition system with H.264 hardware encoding WHAT YOU GET Clean, documented RTL, a reproducible Vivado project with TCL scripts, simulation testbenches, hardware debug support and clear communication. TOOLS Verilog, VHDL, Vivado, Vitis, ILA, Python, C, TCL, AXI4 / AXI-Stream, PCIe, MIPI CSI-2 Tell me your board, interface and target performance, and I’ll give you an honest view of feasibility and approach.