Bhargav S.

As an experienced RTL Design Engineer, I offer extensive expertise gained from working on various projects. I am proficient in multiple communication protocols, including AXI, AHB, APB, SPI, I2C, and USB. My skills extend to managing complex multi-clock designs, with a strong understanding of Clock Domain Crossing (CDC) and timing constraints. I also have experience with the MIPI protocol for camera applications and have worked extensively with Lattice CrossLink-NX boards, as well as a range of Xilinx FPGA boards. My background equips me to deliver high-quality RTL designs and make significant contributions to complex semiconductor projects.