Fatima S.

With over 11 years of experience in FPGA design and digital systems, I have worked on mission-critical aerospace and telecommunications projects, developing FPGA-based solutions from system requirements and architecture through RTL implementation, verification, hardware integration, and debugging. My background includes more than a decade at SUPARCO, where I contributed to the development and deployment of the PakTES-1A satellite system. I hold an MS in Telecommunications Engineering and have extensive experience in FPGA-based digital signal processing, high-speed data processing, communication systems, image processing, and hardware integration. ### FPGA Design & High-Speed Digital Systems I work with Verilog, VHDL, and SystemVerilog using Xilinx Vivado, Intel Quartus, and ModelSim. My experience includes: * FPGA datapath and architecture design * High-speed serial and parallel data paths * SERDES and FPGA transceiver-based designs * PCS/PMA concepts and high-speed transceiver integration * Clock Domain Crossing (CDC) and clock-domain management * Clock and reset architecture * Clock Data Recovery (CDR) concepts and high-speed serial links * Timing analysis, timing constraints, timing closure, setup/hold analysis, and critical-path investigation * FIFOs, asynchronous FIFOs, buffering, and high-throughput data paths * FSMs and control logic * Resource optimization and performance improvement * LVDS and high-speed differential interfaces * UART and I²C interfaces * Camera Link and high-speed camera/data interfaces * TLK-based high-speed communication interfaces * Communication and packetization logic * FPGA-based DSP and image-processing pipelines * Hardware/FPGA integration and board-level debugging I can work from a specification, algorithm, block diagram, schematic, interface description, or existing RTL and help develop, debug, optimize, and verify the FPGA implementation. ### Hardware Debugging & Signal Analysis My experience extends beyond RTL development into practical hardware integration, signal analysis, and troubleshooting. I have worked with **logic analyzers, spectrum analyzers, and Cortex HDR** for hardware and system-level investigation, including analyzing digital and communication signals, verifying interfaces, troubleshooting signal/data issues, and correlating FPGA behavior with external hardware. I am comfortable working across the complete signal path—from FPGA logic and clock domains to transceivers, differential interfaces, external devices, and surrounding hardware. This allows me to troubleshoot problems at both the RTL and system-integration levels. I also use MATLAB, Python, and LabVIEW for algorithm development, modelling, testing, data analysis, and engineering validation. ### Recent FPGA Project I recently worked on a parallel FPGA JPEG-LS encoder, where I refactored the top-level modules, integrated FIFO-based buffering, investigated and resolved output-data issues, and carried out timing analysis to improve the design's performance and meet system requirements. ### Technical Project Management I also have 1.5 years of technical project management experience at SUPARCO, coordinating engineering activities and deliverables. This provided additional experience in technical planning, documentation, engineering coordination, troubleshooting, and taking ownership of projects from requirements through implementation and integration. I approach FPGA projects with a focus on **correct architecture, clean and maintainable RTL, CDC-safe design, reliable timing, efficient resource utilization, robust high-speed interfaces, and practical hardware integration**. Whether you need a complete FPGA implementation, an existing design debugged, a high-speed interface integrated, timing or CDC issues investigated, or an architecture reviewed, I can work from the available technical information and help take the design toward a reliable working implementation.