Bachir F.
Verilog/VHDL RTL Modeling | FPGA | SoC | ASIC | VLSI
FPGA & ASIC Design | UVM Verification | Embedded Systems Offering: RTL development for FPGA/ASIC using SystemVerilog, Verilog, and VHDL UVM verification and simulation with ModelSim/QuestaSim SoC, IP, and embedded system design and prototyping Performance optimization and high-speed development (HFT, HPC) Scripting and automation (TCL, Python) Why Work With Me? With extensive experience in FPGA/ASIC design, UVM verification, and projects involving exascale computing and IP video, I provide expert support in hardware design, verification, and system integration. I am proficient in tools like Vivado, Quartus, and ModelSim, as well as communication protocols (AXI, SPI, I2C, UART). 📌 Available & Responsive | Flexible Pricing | Quality-Driven Approach Let’s discuss your project! 🚀
Earnings and projects
Last 6 months ÷ 6
Billed in all: $1,003$1k
Across 4 contracts