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Bachir F.

Bachir F.

Verilog/VHDL RTL Modeling | FPGA | SoC | ASIC | VLSI

FPGA & ASIC Design | UVM Verification | Embedded Systems Offering: RTL development for FPGA/ASIC using SystemVerilog, Verilog, and VHDL UVM verification and simulation with ModelSim/QuestaSim SoC, IP, and embedded system design and prototyping Performance optimization and high-speed development (HFT, HPC) Scripting and automation (TCL, Python) Why Work With Me? With extensive experience in FPGA/ASIC design, UVM verification, and projects involving exascale computing and IP video, I provide expert support in hardware design, verification, and system integration. I am proficient in tools like Vivado, Quartus, and ModelSim, as well as communication protocols (AXI, SPI, I2C, UART). 📌 Available & Responsive | Flexible Pricing | Quality-Driven Approach Let’s discuss your project! 🚀

🇨🇦Montreal, Canada$40/hr100% JSS4.10 (3)Since Jan 2025

Earnings and projects

MRR
$0

Last 6 months ÷ 6

World#397,352 / 412k
🇨🇦Country#6,973 / 7,133
Revenue, last 30 days
$0
Total earnings
$960

Billed in all: $1k

World#397,352 / 412k
🇨🇦Country#6,973 / 7,133
Per project
$320
Projects, last 6 months
0
World#209,850 / 412k
🇨🇦Country#3,126 / 7,133
Projects in all
3

Across 4 contracts

75% fixed25% hourly
World#304,140 / 412k
🇨🇦Country#5,325 / 7,133

Earnings, last 30 days

$1kNothing earned in the last 30 daysBilled in all, before Upwork's fee · drag across the chart to see what was earned in any stretch
$980$1,000$1,020$1,040Oct 8Oct 23Nov 7

Skills