Petr K.

FPGA top level\IP cores development. Testing and Debugging on FPGA with using ChipScope\Signal Tap, Logical analyzer. Linux driver development for Xilinx Zynq platform. MCU SW development. Skills: Xilinx Vivado and Vitis, Lattice Diamond, Modelsim, Matlab\Simulink FPGAs: Xilinx (Spartan 3,6 Virtex 4,6 Kintex7, Zynq, Artix UltraScale+), Lattice. Interested in: Image sensors, Video\Data analytics on FPGA, Software Defined Radio MCU: 8051 family, Cortex FPGA experience since 2007. Strong knowledge in high-frequency FPGA design, interfaces (DDR3/4, SDRAM, FPGA to FPGA communication, PCIe, CameraLink, Gigabit transceivers), DSP mostly related to SDR (Software Defined Radio). Schematic&PCB design: ADC >1Gsps, DAC >1Gsps, FPGA, STM32, Ethernet, PCIe, SFP, TDC.